INTEL GTL BUFFERS Gunning Transceiver Logic

[FU1G0R]

Una explicaciòn por ahi para los GTL BUFFERS, que encontre, en definitiva algo muy muy interesante para adentrarse al overclock a un niver un poquitin mas hardcore, en definitiva un par de lecturas que cualquier overclocker serio no puede dejar de leer... les dejo con la nota, no la más nueva pero en definitiva una de las mejores explicaciones que en encontrado acerca de los Gunning transceiver logic Buffers Hardcore Stuff

Introduction to A/GTL+ Signaling Conventions


Most Intel processor Front Side Bus (FSB) signals use [Advanced] Gunning Transceiver Logic (A/GTL+) signaling technology. GTL is a standard for electrical signals in CMOS circuits used to provide higher data transfer speeds with smaller voltage swings. (The GTL signal swings between 0.4v and 1.2v with a reference voltage of about 0.8v.) Only a small deviation of 0.4 volts (or thereabouts) from the reference voltage is required to switch between on and off states. Therefore, a GTL signal is said to be a low voltage swing logic signal. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.

Gunning Transceiver Logic has several advantages. The resistive termination of a GTL signal provides a clean signaling environment. Moreover, the low terminating voltage of 1.2 volts results in reduced voltage drops across the resistive elements. GTL has low power dissipation and can operate at high frequency and causes less electromagnetic interference (EMI) and signal line crosstalk than previous solutions.

Intel platforms implement a termination voltage level for GTL+ signals defined as VTT. Because these platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases as the voltage supplies are not coupled. Speed enhancements to data (4x) and address (2x) busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

The A/GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 (low) or a logical 1 (high). GTLREF must be generated on the motherboard (usually derived from VTT by a passive voltage divider network). Termination resistors (RTT) for A/GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most A/GTL+ signals.

Current-generation Intel desktop processor I/O buffers work at a low nominal voltage of about 1.2v (VTT) - an essential element in the reduction of bus power. The bus includes a special automatic resistor compensation method to adjust the buffer strength dynamically during runtime. It accommodates the impacts of temperature, voltage drift, and bus topology (multiple processors and/or chipsets on a single bus). Thus, at any thermal and power state the processor bus has full impedance termination. As stated earlier, Intel processors and chipsets have split power planes that allow setting the I/O operating voltage (VTT) to an independent fixed value even though the CPU may be operating at a higher core voltage (VCC). As overclockers we can use this to our advantage.



Theory of Operation - Increasing Target Performance


VTT, sometimes referred to in the Basic Input/Output System (BIOS) as the FSB Termination Voltage, provides the low level signaling bias needed for the processors, chipsets, and all other devices on the bus to communicate. The FSB is the electrical interface that connects the processor to the chipset (also called the processor system bus or the system bus). All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.

Intel rates the maximum VTT voltage for desktop processors at 1.55v (with respect to VSS). Because undershoot and overshoot specifications become more critical as the process technology for microprocessors shrink due to thinner gate oxide layers; we must note that violating these limits may excessively degrade the life expectancy of the processor and/or chipset. As such, it is important to recognize that any modification(s) that run processor(s) out of specification might results in damage that may not be warrantied by Intel. Don't let this scare you as this is just our standard disclaimer...

http://www.thetechrepository.com/att...1&d=1169411557

Note: Modifications to the circuit are shown in red.

Figure 1 is a simplified diagram illustrating standard bus topology. V(A) can represent any number of devices, such as a second processor die, as is the case with Kentsfield (but not Conroe), and in all cases, the chipset. (This should make sense as Cores 0/1 and Cores 2/3 must communicate via the FSB.) Figure 1 also models how VTT signals are terminated on-die.

Simply raising VTT may or may not create voltage margins necessary to sufficiently skew signals as required to meet minimum sample and hold times for increased bus frequencies. Additionally, processors are particularly sensitive to even small increases in VTT as bus impedances and termination resistance values are quite low. In fact, increasing VTT will most likely just create unwanted device heating with little to no change in FSB stabilization. The more focused approach lies in the tuning of each individual GTL reference level. Each die (note that Kentsfield has two dies) must be supplied with two separate GTL reference levels - one for the data bus and one for the address bus. This means that any board that supports Intel quad-core processors will require four adjustment potentiometers in order to modify all signal switching logic levels. Moreover, motherboards modified with a pair of potentiometers in order to support single-die tuning may not realize the full benefit of this modification when a dual-die processor is installed without first completing all modifications.

Data busses are much more sensitive to adjustments as these lines are consistently more heavily loaded than the address busses. Enterprising enthusiast who wishes to experiment would do much better to modify the data bus GTL reference voltage level(s) before any others. Figure 2 shows the relatively simple modification needed to begin adjusting levels - the potentiometer will allow setting the GTL reference level nearly anywhere from rail to rail (0.4v to 1.2v). Nominal GTL reference voltage for current generation processors/chipsets should be about 2/3 of VTT (or approximately 0.8v), although you may find your board's values a little lower (~0.75v).

http://www.thetechrepository.com/att...1&d=1169090766

Figure 3 shows pad placement of the four (4) GTLREF signal used in the current-generation LGA775 socket platform. Take notice that this is a top-down view and that the image must be horizontally mirrored when viewing the CPU from the bottom. This image is provided so that those that wish to modify their motherboard may do so without the need for hardware specific instructions - by setting a multimeter to measure continuity and then probing these socket pins and components below the socket it is possible to locate modification points on just about any motherboard (circuit shown in Figure 2).

The capacitive nature of devices on the bus along with signal reflection and free wave propagation times lead to what is known as ringback (resonances on the bus as a results of quickly switching signals). Because of this, signals switching from a logical 0 to a logical 1 (and vice versa) do not always immediately and cleanly stabilize at their target pull-up or pull-down voltages. As a result, this ringback can cause either a processor or chipset pin sense voltage to unintentionally cross a GTLREF voltage threshold, creating a undesirable condition in which data corruption may occur, which can quickly manifest itself as instability or even system failure. Figure 4-1 and Figure 4-2 illustrate this point.


http://www.thetechrepository.com/att...1&d=1169236522


Once you begin adjusting GTLREF voltages (for each core data and address bus) you will find that different bus frequencies respond differently to variations in the voltage. This has to do with harmonics and reflected signals as the FSB changes. The best way to make adjustments is by using a "Clockgen" program from inside the OS to set a previously unstable FSB frequency while simultaneous moving the GTLREF voltage points. Memory or data intensive applications (such as Super PI) will stress the system the most. This inherent variation in system response and stability while passing through different ranges of FSB is most likely the reason that some users experience what they describes as "FSB holes." Just because the FSB signal timings are tuned for 350MHz and 450Mhz doesn't necessarily mean that they are adequate for 400Mhz FSB. Figure 5 illustrates this concept graphically.


http://www.thetechrepository.com/att...1&d=1169078346



The following, Figure 6, demonstrates why this modification is important. Without installing the biasing potentiometers vGTLref remains coupled to VTT making it impossible to adjust them independently. With the modification(s) installed the user has complete control over both VTT and vGTLref (an option that is actually included in the BIOS of the new DFI LANPARTY UT ICFX3200-T2R/G motherboard based on the AMD/ATI RD600 chipset)!

http://www.thetechrepository.com/att...1&d=1169080602

SOURCE:

http://www.thetechrepository.com/arc....php?t-87.html

[FU1G0R]

... Continued

Por aca un poco de información extremadamente buena acerca de el voltaje terminal VTT, en lo personal ésto es algo de lo que más recomiendo tocar a la hora de alcanzar estabilidad en plataformas intel, pequeño pero buenisimo el site, incluso incluy gtl buffers info y otras cositas aplicables a muchas boards


Understanding GTL Reference Voltage

Because of the popularity of Intel quadcore processors the method of overclocking has somewhat changed. Most everyone knows that when the CPU and board are pushed to the edge success will hinge on the adjustment of CPU and Northbridge GTL Reference voltages. As important as these settings are to a stable overclock few users know what is being accomplished when these values are changed. For most users, both as to why they need adjusting and how to go about finding the correct values, these settings are shrouded in mystery. GTL (Gunning Transceiver Logic) was invented in 1991 by William Gunning while at Xerox. It was created because of the need for a faster chip-to-chip interface. It is an open-drain, low power switching circuit. Today there are several variations of this specification in use. They differ primarily in the voltages used, signal edge enhancements and slew rates. In the past Intel used a bus technology known as GTL+. The major difference between GTL and GTL+ is that the noise margin around VREF was increased. Currently Intel is using AGTL+ (Assisted Gunning Transceiver Logic +). The most notable difference between AGTL+ and GTL+ is the addition of an active pMOS pull-up transistor on the output of the driver. This is to assist the termination resistors during the first clock of a low-to-high voltage transition. Throughout the following examples all references will be based on the AGTL+ specification. By substituting the correct voltages these examples are valid for most versions of GTL.


Definition of terms used in this article.


VTT is the termination voltage. It is also the voltage VREF is derived from.
VTT(min) is the minimum termination voltage.
VREF is the reference voltage. Normally 2/3(VTT)
VIH (min) is the minimum specified valid input high level voltage. For this example it is 100mV above the reference voltage.
VIL (max) is the maximum specified valid input low level voltage. For this example it is 100mV below the reference voltage.
VOH (min) is the minimum output high level voltage. VOH(min) is equal to VTT(min).
VOL (max) is the maximum output low level voltage. This value is equal to 1/3(VTT).
VTT sets the base voltage levels between ground and itself for the entire GTL circuit with the exception of the threshold voltage. VOL (max) is VTT(1/3) and VREF is VTT(2/3). A change to VTT also changes all the other voltage limits of the circuit. Increasing VTT not only strengthens the signal but also acts as a rather course control for what GTL Reference voltage is normally used for.


Overshoot (sometimes referred to as undershoot for falling transitions), is the amount by which the signal's voltage level extends above or below VTT or ground. Limiting overshoot is necessary to insure the flight time meets the design requirements and to avoid damaging the components connected on the GTL bus
Ringback is the amount by which a signal rebounds below the logic high lower limit (or above the logic low upper limit) after an overshoot event has occurred. Ringback must be limited to prevent inadvertent false switching of these digital signals.
Settling time is a measurement of oscillations on the GTL waveform (usually caused by reflections on the transmission line traces). This term measures the amount of time required for oscillations to dampen to a level that will not increase the flight time of the next transition.



GTL designs like most electronic circuits are optimized for a particular range of operating parameters. This is complicated by the fact that the majority of the circuitry is contained in the processor and chipset. Intel designs these circuits for stock operating speeds and voltages. Motherboards built with overclocking in mind can have this point of optimization shifted somewhat by the board manufacturer with board component selection and design. However there is a limitation to what the manufacturers can accomplish. Not only does the board still need to be stable at stock speeds but well below stock if such options as C1E are utilized. The board also has to come in at a predetermined price-point.

Most GTL designs are built around a differential amplifier that is used as a comparator. A differential amplifier is capable of outputting a preset voltage based on two input voltages. A differential amplifier is used because of its narrow threshold regions ensuring a sufficient noise margin with respect to output swing. One input is tied to VREF. This voltage is what the input is compared to and also is what VIH(min) and VIL(max) (VREF +/- the Threshold voltage) are derived from. The other input receives the incoming signal. If the voltage is below VIL(max) it is considered a logic low and if it is above VIH(min) it is a logic high. Based on these inputs the output will be equal to either VTT or ground. The input side of the differential amplifier is called the receiver and the output side is the driver.



GTL circuits are based on an open-drain output. An open-drain output is one that either sinks current or is at a high impedance. It is never the source of current. The output is connected to VTT through the termination resistor. When the output is in a low (logic 0) state it provides a path to ground for VTT and the bus is pulled low. When the output signal is required to be high (logic 1) the output stops conducting current and the bus returns to the voltage level of VTT. Two of the advantages of an open-drain configuration are its low-power requirement by not having to supply the high state current and the ability of multiple devices to communicate on the same bus.

Overclocking, by increasing voltages and speeds, alters the optimization of the circuits. Increasing voltage changes the impedance of the circuit and the amount of noise that is present. The consequence of this is an increase of overshoot, ringback and settling time. This results in both an improper representation of the data and an increased flight time necessitating the need for a wider timing window. Increasing the speed requires corresponding tighter timing windows. So voltage and speed are a compromise as what satisfies one is detrimental to the other.

Another issue that most users are unaware of is the relationship between VCORE and VTT. To reduce the amount of ringing at the driver, Intel has added a weak pull-up device to the output buffer as mentioned above. This device turns on at the beginning of a low-to-high signal transition, substantially reducing the impedance mismatch between the output buffer and the transmission line. As a result, the amount of overshoot and ringback is significantly reduced. The source terminal of the pull-up device is connected to the core voltage supply. This causes the logic high voltage to rise above the GTL termination voltage for one cycle. After one bus cycle, the pull-up device is turned-off and the output will stabilize at VTT if the output remains in the logic high state. But when we raise VTT above VCORE we have effectively removed the pull-up device from the circuit.

As has been stated above the high level output is VTT. The low level output is ground (0.00 volts) An output signal that extends into the area between VOL(max) and VIL(min) or VTT(min) and VIH(max) can result in the input voltage not being read correctly.

The receiver side has similar constraints. The low level input must be kept between 0.00 volts and VIL(max). The high level input has a range of VIH(min) and VTT. An input voltage level that crosses either VIL(max) or VIL(min) renders the receiver incapable of determining if the signal is a logic high or low.



The area in the figure below between VOL(max) and the dashed line is the Low Level Threshold Voltage. The area between VTT(min) and its corresponding dashed line is the High Level Threshold Voltage. These voltage ranges act as a buffer protecting the input from being corrupted. The Input Threshold Voltage prevents the input level from being misread as its complimentary signal or as undetermined.



Seldom is there a need for adjusting GTL Reference voltages to correct the output of the circuit. Proper resistor termination values along with maintaining minimum stub lengths of the onboard circuitry is usually enough to keep overshoot and ringback in check at the speeds we push for. Other issues that would affect the integrity of the output signal are countered by the increased VTT or VCORE voltage that is already being used by the time a need for GTL Reference voltage adjustments become a necessity.

[FU1G0R]

Continued

as ground bounce is an issue that gtl circuits are susceptible to we'll use it as an example of how changing gtl reference voltages provides a work-around. The faster an output device switches the higher the transient currents become that are seen by the input of the receiver. As a result, the device ground rises (bounces) in relation to the board ground. The ground bounce is generated during the low-to-high signal transition.

The following oscilloscope screenshot shows an output signal in the top trace and a receiver input at device ground potential in the bottom trace. The ground bounce is easily seen as the output signal switches from high to low. If this bounce is severe enough that it crosses vil(max) the gtl circuit may see this as logic high and the output will switch accordingly. A bounce can also be seen when the driver is switching from low to high. This is the result of minor switching current within the device and is so small as to be of no consequence.



the following waveform shown on the left illustrates a failed overclock. Because of the ground bounce the receiver is no longer able to determine the state of the input. The fix is readily apparent since the error can actually be seen. As displayed in the waveform on the right, shifting vref slightly upwards, which results in vil(max) also raising, moves the input signal back into the valid vil range.



So why not just add some extra GTL Reference voltage to begin with as a safety margin? Because VIH needs to be kept within its operating parameters also. The high level input is subject to the same type of signal degradation as the low level input is.

In the waveform below we have the same low level input as in the above example. The top trace shows the input when it's held high. VIH presents no issue concerning stability as it's within its proper operating range. Even when we correct VREF to make VIL a valid signal VIH remains within its operating range.



But what happens if we take the approach that if some adjustment is good more must be better? As the next figure shows, by increasing VREF beyond what is necessary brings VIL even further into its ideal operating range. But by doing so we have created the same type of out-of-spec condition for VIH that was originally affecting VIL.



The following example illustrates the importance of proper GTL Reference voltage adjustment. Prime95 was run with identical settings in both screenshots except for the adjustment of CPU GTL Reference voltages. CPU GTL Reference was set to default in the first screenshot. From previous measurements this value is 108/110. Prime failed in approximately 47 minutes.

In the second screenshot CPU GTL Reference voltage was set at 112/112. Prime95 ran for almost 13 hours before it was manually stopped.





This article has barely touched on the actual design or execution of GTL circuitry. There are many other factors that come into play affecting the signal integrity of a GTL circuit as well as the relationship of the input signal to the output signal. These go far beyond the level of complexity of this article.

While the brute force approach will satisfy some users, those looking for a maximum stable overclock with the minimum amount of voltages will find GTL tuning a necessity. As should now be evident, there is no dark secret or art to adjusting GTL Reference voltages. With a basic understanding of how the circuit functions and the relationship of the voltages used, mastering these settings should be within the capabilities of everyone

TOMADO DE

SOURCE

http://www.edgeofstability.com

[Rayzl]

Muy buena info FU1G0R, y si esta hardcore la info... con mas tiempo la leere toda...

[Israfel]

Mano que buenisima info, con todo y graficas de señales, de verdad va bastante a fondo con relacion a los voltajes que usan los procesadores

[Kdjo]

es lo mismo que encontré aquí... pero sinceramente, me cuesta entenderlo pero es menester ponerlo en práctica.

http://www.thetechrepository.com/showthread.php?t=87

y aquí encontré una "herramienta" (un formato en excel con las fórmulas para calcularlo de una vez ) pero no estoy seguro si está del todo correcto, aunque si lo he probado pero no noto diferencia :S. para quienes quieran probarlo está al final de la "explicación" del siguiente link.

http://www.xtremesystems.org/forums/showthread.php?t=202292

si alguien encuentra un método mas claro, resumido y sencillo le encargo porque aún me cuesta esta cosa

[Kdjo]

hasta que al fin le voy agarrando el hilo a estas cosas jaja pero mas que leer hay que tocarlos y practicar, y solo así vas conociendo el comportamiento de estos :S

después de probar varios programas... puedo decir que prime es el único casi, que en verdad es casi completo para comprobar la estabilidad del micro en muchos sentidos

[abnermkd]

Fulgor, como siempre buena onda por la info. Muy bien detallada. La vamos a leer.

[CharlesMauldin]

Hello all,
I've merely registered this web site
There are some excellent articles here to learn